Currently, graphics controllers/accelerators such as the Intel 740 supports local memory interface from 66.67 MHz to 100 MHz. A typical graphics controller/accelerator such as the Intel 740 has its own local memory that uses either single data rate synchronous dynamic random access memory (SDR-SDRAM) devices or dual data rate synchronous dynamic random access memory (DDR-SDRAM) devices. SDR-SDRAM devices operate according to the “PCSDRAM-100” specification. PCSDRAM-100 specifies data transfers at a maximum transfer rate of 100 MHz. As DRAM vendors move their silicon to next generation processes (≦0.25μ), the capability to produce higher frequency SDRAM devices will increase.
A diagram of a phase locked loop (PLL) circuit is shown in FIG. 1 that illustrates the generation of two clock signals, oCLK and iCLK. The oCLK is used for external DQ I/O clocking and iCLK is used internally for clocking control signals. The iCLK is oCLK plus a delay equal to period of the Fvco of the PLL. This allows for adding a fixed PLL delay to the iCLK. This fixed delay is relatively insensitive to changes in process, temperature and voltage.
FIG. 1 shows various fixed PLL delays at corresponding frequencies. At 100 MHz, N/M is 9/2 and 1/P is 1/3 which gives a PLL delay of 3.3 ns. FIG. 2 illustrates a local memory I/O configuration in a typical graphics controller/accelerator such as the Intel 740. The oCLK is used to generate tCLK and rCLK. The tCLK (transmit clock) is sent to the SDRAM and rCLK (receive clock) is used to latch the incoming data from SDRAM. By routing rCLK to add delay on the motherboard the incoming data can be provided enough setup and hold margins at frequencies between 66.66 MHz and 100 MHz. This currently yields approximately a 1.2 ns of margin on the data window.
By increasing the frequency beyond 100 MHz, even though the data window is maintained, setup is violated while more margin is given to the hold. This problem is shown in FIG. 3. The calculations assume the best case layout and loading conditions.
In order to ensure valid data latching for high speed data transfer (e.g., at higher frequencies than 100 MHz), it is necessary to center the data window around the point of sampling which uses rCLK in this case. One way to center the rCLK is to change its trace length. However, trace length increases are not programmable and more importantly do not provide granularity of control under 1 ns.